mode

AD converter mode.

- SINGLE (default mode for a single conversion)

- FREE. In FREE mode a new conversion cycle is started immediately after a previous conversion has completed.

runmode

Possible values:

ENABLED : In Standby sleep mode, the peripheral continues operation

DISABLED : In Standby sleep mode, the peripheral is halted

res

The resolution of the conversion. Valid values are :

- 8BIT

- 10BIT. This is the default

adc

ENABLED or DISABLED.

By default the AD converter is DISABLED.

samp_acc

This value selects how many consecutive ADC sampling results are accumulated automatically.  Possible values :

- 0 :  (accumulation disabled, default value)

- 2, 4,8,16,32,64 : number of accumulated samples.

samp_cap

Sample capacitance selection.

Possible values :

- BELOW_1V : Recommended for reference voltage values below 1V.

- ABOVE_1V : Reduced size of sampling capacitance. Recommended for higher reference voltages.

samp_dly

Sampling Delay Selection : Numeric constant between 0 and 15.

These bits define the delay between consecutive ADC samples. The programmable Sampling Delay allows modifying

the sampling frequency during hardware accumulation, to suppress periodic noise sources that may otherwise disturb the sampling. The SAMPDLY field can be also modified automatically from sampling cycle to another, by setting the ASDV bit. The delay is expressed as CLK_ADC cycles and is given directly by the bitfield setting. The sampling cap is kept open during the delay.

samp_len

Sample Length. Numeric constant between 0 and 31.

These bits extend the ADC sampling length in number of CLK_ADC cycles. By default the sampling time is two CLK_ADC cycles. Increasing the sampling length allows sampling sources with higher impedance. The total conversion time increased with the selected sampling length.

ref

Voltage Reference selection. Possible values :

- INTERNAL : internal reference. See CONFIG VREF

- VDD : VDD

prescale

Prescaler selection. This is the division from the peripheral clock to the ADC clock. Possible values :

2,4,8,16,32,64,128,256

init_dly

Initialization delay. These bits defines the initialization/startup delay before the first sample when enabling the ADC or changing to

internal reference voltage. Setting this delay will ensure that the reference, muxes, etc are ready before starting the first conversion. The initialization delay will also take place when waking up from deep sleep to do a measurement.

The delay is expressed as a number of CLK_ADC cycles.

Possible values :

- 0   : Delay 0 CLK_CYCLES (no delay)

- 16 : Delay 16 CLK_CYCLES

- 32 : Delay 32 CLK_CYCLES

- 64 : Delay 64 CLK_CYCLES

- 128 : Delay 128 CLK_CYCLES

- 256 : Delay 256 CLK_CYCLES

asdv

Automatic Sampling Delay Variation. ENABLED or DISABLED.

Selecting ENABLED, enables automatic sampling delay variation between ADC conversions. The purpose of varying sampling instant is to randomize the sampling instant and thus avoid standing frequency components in frequency

spectrum. The value of the SAMPDLY bits is automatically incremented by one after each sample.

When the Automatic Sampling Delay Variation is enabled and the SAMPDLY value reaches &HF, it wraps around to 0.

win_cmp

Window Comparator Mode.

This field enables and defines when the interrupt flag is set in Window Comparator mode. RESULT is the 16-bit accumulator result. WINLT and WINHT are 16-bit lower threshold value and 16-bit higher threshold value,

respectively. Possible values :

- NONE : No windows comparison (default)

- BELOW : result < WINLT

- ABOVE : result > WINHT

- INSIDE : WINLT < result  < WINHT

- OUTSIDE : result < WINLT or result > WINHT

mux

Mux position. This bit field selects which single-ended analog input is connected to the ADC. If these bits are changed during a conversion, the change will not take effect until this conversion is complete.

Possible values :

- GND : 0V, GND

- TEMPSENSE : Temperature sensor

- INTREF : Internal reference (from VREF)

- DAC0 : DAC0 output

0-11  : ADC input pin 0-11